Kaisheng Ma

Latest

Cocco: Hardware-Mapping Co-Exploration towards Memory Capacity-Communication Optimization
A Scalable Multi‑Chiplet Deep Learning Accelerator with Hub‑Side 2.5D Heterogeneous Integration
PHEP: Paillier Homomorphic Encryption Processors for Privacy Preserving Applications in Cloud Computing
A 28nm 68MOPS 0.18μJ/Op Paillier Homomorphic Encryption Processor with Bit-Serial Sparse Ciphertext Computing
YOLoC: Deploy Large-Scale Neural Networks by ROM-based Computing-in-Memory using Residual Branch on a Chip
Finding the Task-Optimal Low-Bit Sub-Distribution in Deep Neural Networks
NN-Baton: DNN Workload Orchestration and Chiplet Granularity Exploration for Multichip Accelerators
A 400MHz NPU with 7.8 TOPS²/W High-Performance-Guaranteed Efficiency in 55nm for Multi-Mode Pruning and Diverse Quantization Using Pattern-Kernel Encoding and Reconfigurable MAC Units
PCNN: Pattern-based Fine-Grained Regular Pruning Towards Optimizing CNN Accelerators
SCAN: A Scalable Neural Networks Framework Towards Compact and Efficient Models